1. Field of the Invention
This invention relates to a process for manufacturing a semiconductor integrated circuit device. In particular, it relates to a hydrotreating process for improving device properties and reliability.
2. Description of the Related Art
In a conventional process for manufacturing a semiconductor integrated circuit device such as a memory and a logic, a variety of device structures are formed on a substrate, an interlayer insulating film is deposited and then the product is hydrogen-annealed at about 400.degree. C. in an atmosphere of hydrogen.
The hydrogen-annealing is conducted for improving electric connection properties between metal lines or between a silicon substrate and a metal line, improving device properties and reliability, and improving an yield during the manufacturing process, and thus, is a very important treatment in manufacturing a semiconductor integrated circuit device.
For example, in a DRAM, there exists an interface state between a silicon oxide film (e.g., a device-isolating oxide film and a gate oxide film) and a silicon substrate. Via this interface state, a leak current passes from a diffusion layer to the substrate, which causes deterioration in hold properties of the DRAM. Furthermore, such an interface state causes variation of transistor properties such as a threshold voltage and current-voltage properties, leading to their deviation from design limits. It, therefore, leads to a poor yield of a reliable semiconductor integrated circuit device.
It is believed that an interface state which may cause such various problems may be formed due to a dangling bond in silicon near an interface between a silicon oxide film and a silicon substrate. Hydrogen annealing may supply hydrogen to the interface, and the hydrogen can terminate the dangling bond, which leads to reduction in interface states.
Thus, since hydrogen annealing can stabilize transistor properties such as a threshold voltage and current-voltage properties, it has been also used for a semiconductor integrated circuit other than a DRAM such as a logic.
However, a semiconductor integrated circuit device has become increasingly finer, more compact and more multilayered. In addition, new types of multilayer structure, electrode or electric-line material and insulating material have been increasingly utilized. It has been, therefore, difficult to allow hydrogen to sufficiently penetrate to and diffuse in a target interface by hydrogen annealing. Thus, annealing must be conducted for a longer period at a higher temperature. However, a longer annealing period may reduce productivity. Furthermore, since hydrogen annealing must be conducted in a final manufacturing stage after forming metal lines such as an aluminum line, an excessively higher temperature may lead to poor reliability due to spikes and/or hillocks in a metal line material such as aluminum.
Permeability of hydrogen varies depending on constituents in a semiconductor integrated circuit device, Specifically, hydrogen can penetrate a silicon oxide film such as an interlayer insulating film and a device-isolating insulating film, while not substantially penetrating a silicon nitride film which is frequently used as, for example, an etching stopper, a capacitor insulating film or an anti-contamination film. In particular, a silicon nitride film formed by a low pressure CVD process may act as a diffusion barrier to hydrogen because of its quite dense structure. A metal line material such as aluminum, a barrier metal material such as Ti and TiN and a polycrystalline silicon used for a variety of lines or electrodes can absorb and consume hydrogen. Thus, although hydrogen can penetrate them after reaching a saturation absorption, a diffusion rate may be significantly reduced.
Next, infiltration of hydrogen from the rear face of a substrate will be discussed. As a wafer aperture has become larger, a wafer has become thicker; for example, a thickness is 675 .mu.m for a 6 inch substrate, 725 .mu.m for an 8 inch substrate and more than 770 .mu.m for a 12 inch substrate. Such increase in a thickness means increase of a diffusion distance for hydrogen, which makes it difficult for hydrogen to diffuse from the substrate rear face. Furthermore, during forming a polycrystalline silicon film or silicon nitride film in a device formation process on a substrate surface, there may be also formed or deposited a barrier film to hydrogen diffusion on the rear face, which inhibits infiltration of hydrogen from the rear face. In some cases, a polycrystalline silicon film is intentionally formed on a substrate rear face for EG (Extrinsic Gettering). As discussed above, it is difficult for hydrogen to infiltrate from a substrate rear face, and furthermore, a longer diffusion distance after infiltration may require hydrogen annealing at a higher temperature for a longer period.
With reference to a specific device structure, it will be described that hydrogen annealing has become difficult in a recent device structure.
FIG. 1 shows a plan view and cross sections for an exemplary stack type of DRAM. In this structure, a device-isolating film 2 is formed on a P-type silicon substrate 1 having a given crystal orientation. On the substrate, there is formed a gate insulating film 4 (a silicon oxide film), on which is formed a gate electrode 3 consisting of an N-type polycrystalline silicon film and a tungsten silicide film (unshown) on which a silicon nitride film 6 is deposited. An N-type diffusion layer 5 is formed, which is self-aligned to the device-isolating film and the gate electrode. A silicon nitride film 6 is formed on the side wall of the gate electrode. There is formed a pad 9 consisting of an n-type polycrystalline silicon between the gate electrodes by an anisotropic selective epitaxial growth technique. On these elements, there is deposited an interlayer insulating film 7 in which a contact hole reaching the upper surface of the n-type polycrystalline silicon pad 9 is formed. The contact hole is filled with an N-type polycrystalline silicon, providing a contact 8 electrically connecting with a capacity lower electrode 10. On the capacity lower electrode consisting of an N-type polycrystalline silicon is formed a capacity insulating film 11 consisting of ONO (oxide film-nitride film-oxide film), on which is formed a capacity upper electrode 12 consisting of an N-type polycrystalline silicon. A bit line (unshown) is disposed on the capacity upper electrode, via an interlayer insulating film. A capacity lower electrode 10 is separately formed for each transistor, while a capacity upper electrode 12 is separately formed for each cell array.
In this structure, hydrogen infiltrating by hydrogen annealing is first absorbed by the bit line consisting of the polycrystalline silicon and then absorbed and consumed by the polycrystalline silicon layer constituting the capacity upper electrode 12 formed per a cell array. Then, it reaches an interface between the substrate 1 and the gate insulating film 4 or the device-isolating insulating film 2 via the interlayer insulating film 7. When a bit line is disposed between the capacity lower electrode 10 and the transistor, i.e., a capacitor overbit line (COB) structure, hydrogen can be also absorbed and consumed by a polycrystalline silicon layer constituting the bit line.
Thus, recent tendency to miniaturization and densification have increased a proportion of bit lines and word lines in a unit area and have reduced a distance between cell arrays, which has increasingly made hydrogen annealing difficult.
In particular, in a 16 M type comprising a capacitor underbit line (CUB) structure, there is formed an aperture for contact between a bit line and a substrate diffusion layer, and the aperture is an important diffusion path for hydrogen. However, for a miniaturized 16 M shrink type comprising a COB structure, such an aperture is not necessary. A gap between capacity upper electrodes is a sole diffusion path for hydrogen. A 64 M type or 64 M shrink type is further miniaturized and densified and therefore, a distance between bit lines, between word lines and between capacity lower electrodes is much more reduced.
FIG. 2 schematically shows a cross section for a stack type of DRAM comprising a self-align contact (SAC) structure. In this structure, a silicon nitride film 6 is formed for protecting a gate electrode 3 and a device-isolating film 2 during forming a contact hole, and the silicon nitride film only over the contact is removed before filling the hole. On the other hand, a nitride film is formed or deposited on the substrate rear face during forming the nitride film on the front surface. In such a structure, the substantially whole surface of the substrate is covered by a silicon nitride film which blocks hydrogen. Thus, hydrogen annealing is quite difficult.
FIGS. 3 and 4 show change in a leak current vs a hydrogen annealing time when a silicon substrate having the above structure was hydrogen-annealed by a conventional process, where hydrogen annealing was conducted at 400.degree. C. in an atmosphere of hydrogen/nitrogen (1:1) under an ambient pressure. A leak current was measured while connecting the transistors of all the unit cell blocks in parallel.
FIG. 3 shows measuring results for a stack type of DRAM comprising the structure shown in FIG. 1, indicating that the more densified, i.e, sequentially from (a) a 16 M type comprising CUB structure, (b) a 16 M shrink type comprising COB structure, (c) a 64 M type comprising COB structure to (d) a 64 M shrink type comprising COB structure, the longer time is taken for reducing a leak current and thus the longer period is required for hydrogen annealing.
FIG. 4 shows the measuring results for a 64 M stack type of DRAM (b) comprising an SAC structure together with the results for that (a) not comprising an SAC structure. This figure indicates that for (b) the DRAM comprising an SAC structure, a leak current is not significantly reduced, i.e., hydrogen does not substantially infiltrate or diffuse.